Verilog 1

Synthesizable vs Nonsynthesizable

There are two parts to Verilog — synthesizable and nonsynthesizable. The synthesizable part models real hardware where the nonsynthesizable part does not model real hardware and is instead the logic used for testing.

Values

There are four possible values in Verilog:

• Logic 0
• Logic 1
• X (undefined behavior or that the value could be either zero or one)
• Z (floating)

Basic Building

You can declare wire, in this case names ‘a’ with wire a;.

You can also define various gates. The first item is the output wire and the successive items are inputs. For example not(y, a) is a NOT gate with the input a and output y. You should declare wires first (at the very least for neatness and clarity), but gates can be declared in any order.

There are also modules that contain a group of behavior.