ECE 2300
- from: Jakob Nacanaynay <jn567@cornell.edu>
- to: You <anyone@out.there>
- date: August 26, 2025, 6:59 PM
- subject: ECE 2300
Coursework
- MOSFETs
- Digital CMOS Circuits
- Delay Models
- Combinational Logic
- Verilog 1
- Propagation and Contamination Delay Model
- Boolean Algebra
- Karnaugh Maps
- [Encoder and Decoder]
- [Priority Encoder]
- [Multiplexer and Demultiplexer]
- [Shifters]
- [Rotators]
- [Comparators]
- [Basic Adders]
- Carry-Select Adders
- Carry-Lookahead Adders
- [RTL Modeling]
- [Twos Complement]
- [Floating Point]
Verilog Adventure
- [Logic Gates]
- [Adders]
- [Multiplexer]
- [Decoder]
- [SR Latch]
- [D Flip-Flop]
- [Register]
- [Enabled Flip-Flop]
- [Resettable Flip-Flop]
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~ Jakob Nacanaynay
(nack-uh-nigh-nigh)
he/him/his